1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device including stacked capacitors, and more particularly to a method for fabricating a semiconductor device including stacked capacitors, which is capable of effectively reducing a topology resulting from those stacked capacitors.
2. Description of the Related Art
As well known, the recent trend to fabricate a semiconductor device with a high degree of integration inevitably results in a reduced cell size. Such a semiconductor device has a stacked capacitor structure having an increased stack height in order to obtain a desired capacity in the reduced cell size. Due to such an increased stack height, there is a severe topology between a RAM cell region formed with capacitors and a logic circuit region around the RAM cell region, as shown in FIG. 1. In FIG. 1, the reference character xe2x80x9cAxe2x80x9d denotes the logic circuit region, and the reference character xe2x80x9cBxe2x80x9d denotes the RAM cell region.
In the logic circuit region A arranged around capacitors, the semiconductor device has a reduced line width and a narrow line space due to a high degree of integration thereof.
Such a semiconductor device also has a multi-layered line structure in order to obtain an increased integration efficiency. Due to such a multi-layered line structure, the number of interconnection lines adapted to electrically connect lines of multi-layers together must be increased.
For the high degree of integration in such a semiconductor device, accordingly, it is required to form a pattern having an increased accuracy in the logic circuit region A. Furthermore, it is difficult to conduct a patterning process for layers formed following the formation of capacitors because the topology caused by the structure of those capacitors becomes severe.
That is, a severe topology is generated between the RAM cell region B formed with capacitors and the logic circuit region A formed with a logic circuit due to an increased stack height of the capacitor structure. Due to such a severe topology, it is impossible to form an accurate pattern in the logic circuit region A or RAM cell region B. This is because when a particular layer formed on the capacitor structure is patterned in accordance with a photolithography process, there is a focus depth difference between exposure light onto the logic circuit region A and exposure light onto the RAM cell region B.
The present invention has been made in view of the above mentioned problems, and an object of the invention is to provide a method for fabricating a semiconductor device including stacked capacitors, which is capable of effectively reducing a topology formed between a logic circuit region and a RAM cell region.
In accordance with the present invention, this object is accomplished by providing A method for fabricating a semiconductor device including stacked capacitors on a semiconductor substrate having a logic circuit region formed with a circuit and a RAM cell region formed with a plurality of transistors, comprising the steps of: forming an insulating film to a thickness corresponding to a height of stacked capacitors, to be formed, over an upper surface of the semiconductor substrate; partially removing the insulating film from the RAM cell region, thereby forming a space in which the stacked capacitors are to be formed; forming the stacked capacitors in the space; and partially removing the insulating film from the logic circuit region, and forming interconnection lines for the logic circuit in a space defined in the logic circuit region by virtue of the removal of the insulating film.